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N-CHANNEL 30V - 0.016 - 18A PowerSO-8TM LOW GATE CHARGE STripFETTM II POWER MOSFET
Table 1: General Features
TYPE STSJ18NF3LL

STSJ18NF3LL
Figure 1:Package
RDS(on) <0.019 ID 18 A
VDSS 30 V
TYPICAL RDS(on) = 0.016 @ 10V TYPICAL Qg = 12.5 nC @ 4.5 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED IMPROVED JUNCTION-CASE THERMAL RESISTANCE PowerSO-8TM
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. This silicon, housed in thermally improved SO-8TM package, exhibits optimal on-resistance versus gate charge tradeoff plus lower Rthj-c. APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCS
Figure 2: Internal Schematic Diagram
DRAIN CONTACT ALSO ON THE BACKSIDE
Table 2: Order Codes
SALES TYPE MARKING PACKAGE
STSJ18NF3LL
18F3LL)
PowerSO-8
PACKAGING TAPE & REEL
Table 3: ABSOLUTE MAXIMUM RATING
Symbol VDS VDGR VGS ID ID IDM(*) Ptot Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C (*) Drain Current (continuous) at TC = 100C(*) Drain Current (pulsed) Total Dissipation at TC = 25C Total Dissipation at TC = 25C (#) Value 30 30 16 18 18 72 70 3
(*) Value limited by wires bonding
Unit V V V A A A W W
(*) Pulse width limited by safe operating area.
March 2005
Rev. 1.0
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Table 4: THERMAL DATA
Rthj-c Rthj-amb Tj Tstg Thermal Resistance Junction-case (*)Thermal Resistance Junction-ambient Maximum Operating Junction Temperature Storage Temperature Max Max 1.8 41.7 150 -55 to 150 C/W C/W C C
(*) When Mounted on FR-4 board with 1 inch2 pad, 2 oz of Cu and t > 10 sec.
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED)
Table 5: OFF
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 30 1 10 100 Typ. Max. Unit V A A nA
IGSS
Table 6: ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 9 A ID = 9 A Min. 1 0.016 0.019 0.019 0.022 Typ. Max. Unit V
Table 7: DYNAMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS=15 V ID = 9 A Min. Typ. 17 800 250 60 Max. Unit S pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0
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ELECTRICAL CHARACTERISTICS (continued)
Table 8: SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 15 V ID = 9 A VGS = 4.5 V RG = 4.7 (Resistive Load, Figure 15) VDD=15V ID=18A VGS=4.5V (see test circuit, Figure 16) Min. Typ. 18 32 12.5 3.2 4.5 17 Max. Unit ns ns nC nC nC
Table 9: SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 15 V ID = 9 A VGS = 4.5 V RG = 4.7, (Resistive Load, Figure 17) Min. Typ. 21 11 Max. Unit ns ns
Table 10: SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM
(* )Pulse
Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
Test Conditions
Min.
Typ.
Max. 18 72
Unit A A V ns nC A
ISD = 18 A
VGS = 0 23 17 1.5
1.2
ISD = 18 A di/dt = 100A/s Tj = 150C VDD = 15 V (see test circuit, Figure 17)
width limited by safe operating area.
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
Figure 3: Safe Operating Area
Figure 4: Thermal Impedance
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Figure 5: Output Characteristics Figure 6: Transfer Characteristics
Figure 7: Transconductance
Figure 8: Static Drain-source On Resistance
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Capacitance Variations
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Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 12: Normalized on Resistance vs Temperature
Figure 13: Source-drain Diode Forward Characteristics
Figure 14: Normalized Breakdown Voltage vs Temperature.
.
.
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Fig. 15 Switching Times Test Circuits For Resistive Load Fig.16: Gate Charge test Circuit
Fig. 17: Test Circuit For Diode Recovery Behaviour
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Table 11:Revision History
Date
March 2005
Revision
1.0 FIRST ISSUE
Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners.
(c) 2005 STMicroelectronics - All Rights Reserved
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